High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking dice vertically and interconnecting the dice using through-silicon (or through-substrate) vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM). There is another type of 3D memory device that is called “Master-Slave Memory”.
For example, the Master-Slave Memory is a type of memory including a plurality of random access memory (DRAM) dies vertically stacked with each other, in which the lowermost one of the DRAM dies serves as a master die and remaining one or ones of DRAM dies serve as a slave die. Refresh operations of the stacked DRAM dies are executed periodically to maintain information stored in each memory cell. Each die executes the refresh operations. The refresh operation may be an auto refresh (AREF) operation periodically executed by a system (e.g., a memory controller) and a self refresh (SREF) operation automatically executed by the DRAM dies. An entry to the self refresh operation causes the stacked DRAM dies to automatically execute periodical refresh operations based on an internal timer and all the stacked DRAM dies execute refresh operations simultaneously. Thus, currents of all the stacked DRAM dies reach their peak values simultaneously due to the self refresh operation of all the slacked DRAM dies. A total of the peak currents increases as a number of the stacked DRAM dies increases. It may be desirable to stabilize internal voltages generated in each die even when all the DRAM dies execute the self refresh operation simultaneously.